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V*I Chip - VTM Voltage Transformation Module
TM
V048K015T80
Vf = 32 - 57.6 V VOUT = 1.0 - 1.8 V IOUT = 80 A K = 1/32 ROUT = 1.5 m max
(c)
1
* 48V to 1.5V V*I Chip Converter * 80 A (120 A for 1 ms) * High density - up to 320 A/in3 * Small footprint - 80 A/in2 * Low weight - 0.4 oz (12 g) * Pick & Place / SMD
* >92% efficiency at 1.5V * 125C operation * 1 s transient response * >3.5 million hours MTBF * No output filtering required * V*I Chip BGA package
Actual size
Product Description
The V048K015T80 V*I Chip Voltage Transformation Module (VTM) breaks records for speed, density and efficiency to meet the demands of advanced DSP, FPGA, ASIC, processor cores and microprocessor applications at the point of load (POL) while providing isolation from input to output. It achieves a response time of less than 1 s and delivers up to 80A in a volume of less than 0.25 in3 while converting 48 V to 1.5 V with unprecedented efficiency. It may be paralleled to deliver hundreds of amps at an output voltage settable from 1.0 to 1.8 Vdc. The VTM V048K015T80's nominal output voltage is 1.5 Vdc from a 48 Vdc input factorized bus, Vf, and is controllable from 1.0 to 1.8 Vdc at no load, and from 0.9 V to 1.7 V at full load, over a Vf input range of 32 to 57.6 Vdc. It can be operated either open- or closed-loop depending on the output regulation needs of the application. Operating open-loop, the output voltage tracks its Vf input voltage with a transformation ratio, K=1/32, and an output resistance, ROUT =1.3 milliohm, to enable applications requiring a programmable low output voltage at high current and high efficiency. Closing the loop back to an input Pre-Regulation Module (PRM) or DC-DC converter may be used to compensate for ROUT.
Absolute Maximum Ratings
Parameter
+In to -In +In to -In PC to -In TM to -In SG to -In +Out to -Out Isolation voltage
Values
-1.0 to 60.0 100 -0.3 to 7.0 -0.3 to 7.0 500
Unit
Vdc Vdc Vdc Vdc mA
Notes
For 100 ms
P
EL R
I IM
Output current Peak output current Storage temperature Output power Peak output power Symbol RJC RJB RJA RJA Notes Parameter Junction-to-case Junction-to-BGA
Operating junction temperature
Case temperature during reflow
RY A N
-0.5 to 5.0 1500 Vdc Vdc C A -40 to 125 80 See note 2 Continuous 120 A For 1 ms 208 C -40 to 150 144 216 C W W Continuous For 1 ms Typ 1.1 2.1 6.5 5.0 Max 1.5 2.5
Input to Output
Thermal Resistance
Units C/W C/W C/W C/W
The 1.5V VTM achieves break-through current density of 320 A/in3 in a V*I Chip package compatible with standard pick-and-place and surface mount assembly processes. The V*I Chip BGA package supports in-board mounting with a low profile of 0.16" (4mm) over the board. A J-lead package option supports on-board surface mounting with a profile of only 0.25" (6mm) over the board. The VTM's fast dynamic response and low noise eliminate the need for bulk capacitance at the load, substantially increasing the POL density while improving reliability and decreasing cost.
Junction-to-ambient 3 Junction-to-ambient
4
7.2
5.5
1. For complete product matrix, see chart on page 10. 2. The referenced junction is defined as the semiconductor having the highest temperature. This temperature is monitored by the temperature monitor (TM) signal and by a shutdown comparator. 3. V048K015T80 surface mounted in-board to a 2" x 2" FR4 board, 4 layers 2 oz Cu, 300 LFM. 4. V048L015T80 (0.25"H integral Pin Fins) surface mounted on FR4 board, 300 LFM.
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V*I Chip Voltage Transformation Module Rev. 1.6 Page 1 of 20
Specifications
INPUT (Conditions are at nominal line, full load, and 25C ambient unless otherwise specified)
Parameter Input voltage range Input dV/dt Input undervoltage turn-on Input undervoltage turn-off Input overvoltage turn-on Input overvoltage turn-off Input quiescent current Inrush current overshoot Input current Input reflected ripple current No load power dissipation Internal input capacitance Internal input inductance Recommended external input capacitance Min 32 Typ 48 Max 57.6 10 32 Unit V V/s V V V V mA A A mA p-p W F nH F Note
29.5 57.6
P
EL R
8
IN IM
2.0 0.7 59.0 2.4 2.7 28 2.5 1 20 100 3.5
PC low Using test circuit in Fig.24; See Fig.1
Y AR
Using test circuit in Fig.24; See Fig.4
200 nH maximum source inductance; See Fig.24
INPUT WAVEFORMS
Figure 1-- Inrush transient current at no load and nominal VIN with PC enabled
Figure 2-- Output voltage turn-on waveform with PC enabled at full load and nominal VIN
Figure 3--Output voltage turn-on waveform with input turn-on at full load and nominal VIN
Figure 4-- Input reflected ripple current at full load and nominal VIN
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V*I Chip Voltage Transformation Module Rev. 1.6 Page 2 of 20
Specifications, continued
OUTPUT (Conditions are at nominal line, full load, and 25C ambient unless otherwise specified)
Parameter Rated DC current Peak repetitive current DC current limit Current share accuracy Efficiency Half load Full load Internal output inductance Internal output capacitance Load capacitance Output overvoltage setpoint Output ripple voltage No external bypass 200F bypass capacitor Average short circuit current Effective switching frequency Line regulation K Load regulation ROUT Transient response Voltage undershoot Voltage overshoot Response time Recovery time Output overshoot Input turn-on PC enable Output turn-on delay From application of power From release of PC pin 80 95 5 93.8 91.7 1.6 300 100,000 1.83 47 2 200 3.0 70 Min 0 Typ Max 80 120 120 10 Unit A A A % % % nH F F V mV mV mA MHz Note Max pulse width 1ms, max duty cycle 10%, baseline power 50% See Parallel Operation on page 11 See Fig.5 See Fig.5 Effective value
93.0 90.8
2.5 0.0309
P
95 94 93 92 91 90 89 88 87 86 85 8 16
EL R
Efficiency vs. Output Current
I IM
1/32 1.3 0.0316 1.5 10 26 200 1 0 0 170 300 250 ms s
3.6
m mV mV ns s
RY NA
See Figs.7 and 10 See Fig.8 Fixed, 1.5 MHz per phase VOUT=K*VIN at no load See Figs.9 and 27 0-80A load step with 100F CIN; See Figs.11 and 12 80-0A load step with 100F CIN See Figs.11 and 12 See Figs.11 and 12 No output filter; See Fig.3 No output filter; See Fig.2
mV mV
OUTPUT WAVEFORMS
Power Dissipation vs. Output Current
12
Power Dissipation (W)
10 8 6 4 2 0
Eficiency (%)
24
32
40
48
56
64
72
80
8
16
24
32
40
48
56
64
72
80
Output Current (A)
Output Current (A)
Figure 5-- Efficiency vs. output current at 1.5V VOUT
Figure 6--Power dissipation as a function of output current at 1.5V VOUT
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V*I Chip Voltage Transformation Module Rev. 1.6 Page 3 of 20
Specifications, continued
PRELIMINARY
Figure 7-- Output voltage ripple at full load and nominal VIN; without any external bypass capacitor.
Figure 8--Output voltage ripple at full load and nominal VIN with 200 F ceramic external bypass capacitance.
Output Ripple vs. Load
50 45 40
Output Ripple (mV)
35 30 25 20 15 10 5 0 8 16 24 32 40 48 56 64 72 80
TBD
Output Current (A)
Figure 9-- Output impedance vs. frequency
Figure 10-- Output voltage ripple vs. output current at nominal line with no POL bypass capacitance.
Figure 11-- 0-80A step load change with 100 F input capacitance and no output capacitance.
Figure 12-- 0-80A step load change with 100 F input capacitance and 100 F output capacitance.
V*I Chip Voltage Transformation Module Rev. 1.6 Page 4 of 20
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Specifications, continued
GENERAL
Parameter MTBF MIL-HDBK-217F Telcordia TR-NT-000332 Telcordia SR-332 Demonstrated Isolation specifications Voltage Capacitance Resistance Agency approvals (pending) Mechanical parameters Weight Dimensions Length Width Height Min Typ 3.6 4.2 TBD TBD 1,500 5,100 10 cTUVus CE Mark 0.43 / 12.25 1.26 / 32 0.85 / 21.5 0.24 / 6 oz / g 6,000 Max Unit Mhrs Mhrs hrs hrs Vdc pF M Note 25C, GB
Input to Output Input to Output Input to Output UL/CSA 60950, EN 60950 Low voltage directive See mechanical drawing, Figs.16 and 18
Auxiliary Pins (Conditions are at nominal line, full load, and 25C ambient unless otherwise specified)
Parameter Primary Control (PC) DC voltage Module disable voltage Module enable voltage Current limit Enable delay time Disable delay time Temperature Monitor (TM) 27C setting Temperature coefficient Full range accuracy Current limit
EL PR
Min 4.8 2.4 2.4 2.95 -5 100
I IM
Typ 5.0 2.5 2.5 2.5 300 4 Max 5.2 2.6 2.9 450 10 3.05 5 3.00 10
in / mm in / mm in / mm
RY NA
Note Source only See Fig.2 Operating junction temperature Operating junction temperature Source only
Unit V V V mA s s
V mV/C C A
Figure 13-- VOUT at full load vs. PC disable
Figure 14-- PC signal during fault
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V*I Chip Voltage Transformation Module Rev. 1.6 Page 5 of 20
Specifications, continued
THERMAL
Symbol Parameter Over temperature shutdown Thermal capacity Junction-to-case thermal impedance Junction-to-BGA thermal impedance Junction-to-ambient 1 Junction-to-ambient 2
PRELIMINARY
Min 125
Typ 130 0.61 1.1 2.1 6.5 5.0
Max 135
Unit C Ws/C C/W C/W C/W C/W
Note Junction temperature
RJC RJB RJA RJA
Notes
1. V048K015T80 surface mounted in-board to a 2" x 2" FR4 board, 4 layers 2 oz Cu, 300 LFM. 2. V048L015T80 (0.25"H integral Pin Fins) surface mounted on FR4 board, 300 LFM.
V*I CHIP STRESS DRIVEN PRODUCT QUALIFICATION PROCESS
Test High Temperature Operational Life (HTOL) Temperature cycling High temperature storage Moisture resistance Temperature Humidity Bias Testing (THB) Pressure cooker testing (Autoclave) Highly Accelerated Stress Testing (HAST) Solvent resistance/marking permanency Mechanical vibration Mechanical shock Electro static discharge testing - human body model Electro static discharge testing - machine model Highly Accelerated Life Testing (HALT) Dynamic cycling Standard JESD22-A-108-B JESD22-A-104B JESD22-A-103A JESD22-A113-B EIA/JESD22-A-101-B JESD22-A-102-C JESD22-A-110B JESD22-B-107-A JESD22-B-103-A JESD22-B-104-A EIA/JESD22-A114-A EIA/JESD22-A115-A Per Vicor Internal Test Specification Per Vicor internal test specification Environment 125C, Vmax, 1,008 hrs -55C to 125C, 1,000 cycles 150C, 1,000 hrs Moisture sensitivity Level 4 85C, 85% RH, Vmax, 1,008 hrs 121C, 100% RH, 15 PSIG, 96 hrs 130C, 85% RH, Vmax, 96 hrs Solvents A, B & C as defined 20g peak, 20-2,000 Hz, test in X, Y & Z directions 1,500g peak 0.5 ms pulse duration, 5 pulses in 6 directions Meets or exceeds 2,000 Volts Meets or exceeds 200 Volts Operation limits verified, destruct margin determined Constant line, 0-100% load, -20C to 125C
V*I CHIP BALL GRID ARRAY INTERCONNECT QUALIFICATION
Test BGA Daisy-Chain thermal cycling Ball shear Bend test Standard IPC-SM-785 IPC-9701 IPC-9701 IPC J-STD-029 IPC J-STD-029 Environment TC3, -40 to 125C at <10 C/min, 10 min dwell time No failure through intermetallic Deflection through 4 mm
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V*I Chip Voltage Transformation Module Rev. 1.6 Page 6 of 20
Pin/Control Functions
+IN/-IN DC VOLTAGE PORTS The VTM input should not exceed the high end of the range specified. Be aware of this limit in applications where the VTM is being driven above its nominal output voltage. An internal over/under voltage lock-out function prevents operation outside of the specified input range. The VTM will turn on when the input voltage rises above the under voltage lock-out specified. If the input voltage exceeds the over voltage lock-out, the VTM will shutdown until the over voltage fault clears. The VTM does not have internal input reverse polarity protection. Adding a properly sized diode in series with the positive input or a fused reverse-shunt diode will provide reverse polarity protection. A minimum 8 F Aluminum Electrolytic capacitor should be applied at the input of the VTM. Additional capacitance, e.g. 100 F, may be added to enhance dynamic performance or to compensate for high source impedance. SG - Signal Ground The Signal Ground (SG) pin provides a Kelvin return for the Primary Control (PC) and Temperature Monitor (TM) ports. Even though the SG pin is referenced to the -IN of the VTM, it should not be used as an additional -IN connection. PC - Primary Control
43 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL 21 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL
+Out
+In
-Out
Temp. Monitor Signal Ground Primary Control
+Out
-In
-Out
Bottom View
Figure 15--VTM BGA configuration
Signal Name +In -In TM SG PC +Out -Out BGA Designation A1-L1, A2-L2 AA1-AL1, AA2-AL2 P1, P2 T1, T2 V1, V2 A3-G3, A4-G4, U3-AC3, U4-AC4 J3-R3, J4-R4, AE3-AL3, AE4-AL4
The Primary Control (PC) pin is a multifunction pin for controlling the VTM as follows:
Enable/Disable - If the PC is left floating or is pulled to logic HI, the VTM output is enabled. To disable the output, the PC pin must be pulled lower than 2.4 V, referenced to SG. Optocouplers, open collector transistors or relays can be used to control the PC pin. The PC port should not be toggled at a rate higher than 1 Hz. Primary Auxiliary Supply - The PC port can source up to 2.4 mA at 5 Vdc.
P
EL R
I IM
RY NA
+OUT/-OUT DC Voltage Output Ports The output (+OUT) and output return (-OUT) are through two sets of contact locations. The respective +OUT and -OUT groups must be connected in parallel with as low an interconnect resistance as possible. Within the specified input voltage range, the Level 1 DC behavioral model shown in Figure 27 defines the output voltage of the VTM. The current source capability of the VTM is shown in the specification table. To take full advantage of the VTM, the user should note the low output impedance of the device as shown in Figure 9. The low output impedance provides fast transient response without the need for bulk POL capacitance. Limited-life electrolytic capacitors required with conventional converters can be reduced or even eliminated, saving cost and valuable board real estate.
Alarm - The VTM contains watchdog circuitry that monitors output overload, input over voltage, input under voltage, or excessive internal temperature. In response to any of these abnormal conditions the PC port will toggle as shown in Figure 14. TM - Temperature Monitor The Temperature Monitor (TM) provides a linear output proportional to the internal temperature of the VTM. At 300K (+27C) the TM output is 3.0 V and varies 10 mV/C. TM accuracy is +/-5C if the SG pin is used as the ground return of the TM signal. This feature is useful for validating the thermal design of the system as well as monitoring the VTM temperature in the final application.
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V*I Chip Voltage Transformation Module Rev. 1.6 Page 7 of 20
Mechanical Drawings
PRELIMINARY
1,00 0.039 1,00 0.039 9,00 0.354
SOLDER BALL #A1
18,00 0.709
SOLDER BALL #A1 INDICATOR
21,5 0.85
6,0 0.24
(106) X o
0,51 0.020
SOLDER BALL
1,00 TYP 0.039
OUTPUT
30,00 1.181
INPUT
INPUT
OUTPUT
32,0 1.26
28,8 1.13 16,0 0.63
C L
15,00 0.591
TOP VIEW (COMPONENT SIDE)
1,6 0.06
C L
BOTTOM VIEW
1,00 0.039
4,0 0.16 NOTES: mm 1- DIMENSIONS ARE inch . 2- UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE: .X/[.XX] = +/-0.25/[.01]; .XX/[.XXX] = +/-0.13/[.005] 3- PRODUCT MARKING ON BOTH TOP AND BOTTOM SURFACES
15,7 0.62
SEATING PLANE
Figure 16--VTM BGA mechanical outline; In-board mounting
IN-BOARD MOUNTING BGA surface mounting requires a cutout in the PCB in which to recess the V*I Chip
0,51 (o ) 0.020
SOLDER MASK DEFINED PADS
1,50 0.059 ( 1,00 ) 0.039 0,50 0.020 o 0,53 PLATED VIA 0.021
CONNECT TO INNER LAYERS
0,50 0.020
( 1,00 ) 0.039 1,00 0.039 9,00 0.354 18,00 0.709 1,00 0.039 1,00 0.039
SOLDER PAD #A1
(2) X 10,00 0.394
+IN
(4) X 6,00 0.236
+OUT1 -OUT1
RECOMMENDED LAND AND VIA PATTERN
TM
(COMPONENT SIDE SHOWN)
PCB CUTOUT
SG
29,26 1.152 24,00 0.945 16,00 0.630 8,00 0.315 0,37 0.015 1,6 (4) X R 0.06 NOTES: mm 1- DIMENSIONS ARE inch . 2- UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE: .X/[.XX] = +/-0.25/[.01]; .XX/[.XXX] = +/-0.13/[.005]
20,00 0.787 17,00 0.669 15,00 13,00 0.591 0.512
+OUT2
-IN
PC
-OUT2
(106) X o
0,51 0.020
8,08 0.318 16,16 0.636
SOLDER MASK DEFINED PAD
Figure 17-- VTM BGA PCB land/VIA layout information; In-board mounting
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V*I Chip Voltage Transformation Module Rev. 1.6 Page 8 of 20
Mechanical Drawings
PRELIMINARY
22,0 0.87
6,2 0.25
3,01 0.118
15,99 0.630
3,01 0.118
(4) PL. 7,10 0.280 OUTPUT INPUT
11,10 (2) PL. 0.437
32,0 1.26
INPUT
24,00 0.945 16,00 0.630 8,00 0.315
TOP VIEW (COMPONENT SIDE)
Figure 18--VTM J-lead mechanical outline; On-board mounting
(2) PL. 11,48 0.452
1,60 (3) PL. 0.063
+IN
PC SG TM
20,00 0.787 16,94 0.667 14,94 0.588 12,94 0.509
-IN
Figure 19-- VTM J-lead PCB land layout information; On-board mounting
OUTPUT NOTES: 1- DIMENSIONS ARE mm/[INCH]. 3,26 0.128 15,74 0.620
(COMPONENT SIDE SHOWN)
C L
12,94 0.509
C L
14,94 0.588
16,94 0.667
20,00 0.787
0,45 0.018
BOTTOM VIEW
2- UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE: .X/[.XX] = +/-0.25/[.01]; .XX/[.XXX] = +/-0.13/[.005] 3- PRODUCT MARKING ON BOTH TOP AND BOTTOM SURFACES
3,26 0.128
RECOMMENDED LAND PATTERN
+OUT1 -OUT1 +OUT2 -OUT2 8,00 0.315
(4) PL. 7,48 0.294
24,00 0.945 16,00 0.630
NOTES: 1- DIMENSIONS ARE mm/[INCH]. 2- UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE: .X/[.XX] = +/-0.25/[.01]; .XX/[.XXX] = +/-0.13/[.005]
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V*I Chip Voltage Transformation Module Rev. 1.6 Page 9 of 20
Part Numbering and Configuration Options
V*I Chip VOLTAGE TRANSFORMATION MODULE PART NUMBERING
V
Voltage Transformation Module
048
Input Voltage Designator
K
Configuration Options F = On-board (Fig.21) G = On-board with 0.25" Integral Pin Fins (Fig.23) K = In-board (Fig.20) L = In-board with 0.25" Integral Pin Fins (Fig.22)
015
Output Voltage Designator (=VOUT x10)
T
Product Grade Temperatures (C) Grade Storage Operating T -40 to150 -40 to125
80
Output Current Designator (=IOUT)
CONFIGURATION OPTIONS
IN-BOARD WITH 0.25" PIN FINS** 178 A/in3 2.1 C/W N/A ON-BOARD WITH 0.25" PIN FINS** 144 A/in3 2.4 C/W N/A
CONFIGURATION Effective Current Density Junction-Board Thermal Resistance Junction-Case Thermal Resistance Junction-Ambient Thermal Resistance 300LFM VTM Model No.
IN-BOARD* 480 A/in3 2.1 C/W 1.1 C/W 6.5 C/W V048K015T80
ON-BOARD* 320 A/in3 2.4 C/W 1.1 C/W 6.8 C/W
*Surface mounted to a 2" x 2" FR4 board, 4 layers 2 oz Cu **Pin Fin heat sink also available as a separate item
EL PR
21.5 0.85 32.0 1.26 4.0 0.16
IN IM
V048F015T80
32.0 1.26
5.0 C/W
V048L015T80
RY A
5.0 C/W V048G015T80
22.0 0.87
6.3 0.25
IN-BOARD MOUNT (V*I Chip recessed into PCB)
mm in
ON-BOARD MOUNT
mm in
Figure 20--In-board mounting - package K
Figure 21--On-board mounting - package F
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V*I Chip Voltage Transformation Module Rev. 1.6 Page 10 of 20
Configuration Options (Cont.)
21.5 0.85
PRELIMINARY
22.0 0.87
32.0 1.26
32.0 1.26
11.7 0.46
14.0 0.56
IN-BOARD MOUNT with 0.25'' Pin Fins (V*I Chip recessed into PCB)
mm in
ON-BOARD MOUNT with 0.25'' Pin Fins
mm in
Figure 22-- In-board with Pin Fins - package L
Figure 23-- On-board with Pin Fins - package G
Input reflected ripple measurement point
F1
7A Fuse
+In
Enable/Disable Switch 0.47 F ceramic
+Out
+
C2
C1
100 F Al electrolytic
2K SW1
R2
PC SG TM -In -Out - VTM
C3
100 F
Load
D1
+ Temperature Monitor - Notes: C3 should be placed close to the load. D1 power good indicator will dim when a module fault is detected. TM should always be referenced to SG.
Figure 24--VTM test circuit
Application Note
Parallel Operation In applications requiring higher current or redundancy, VTMs can be operated in parallel without adding control circuitry or signal lines. To maximize current sharing accuracy, it is imperative that the source and load impedance on each VTM in a parallel array be equal. To achieve matched impedances, dedicated power planes within the PC board should be used for the output and output return paths to the array of paralleled VTMs. This technique is preferable to using traces of varying size and length. The VTM power train and control architecture allow bi-directional power transfer when the VTM is operating within its specified ranges. Bi-directional power processing improves transient response in the event of an output load dump. The VTM may operate in reverse, returning output power back to the input source. It does so efficiently.
V*I Chip Voltage Transformation Module Rev. 1.6 Page 11 of 20
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Application Note (continued)
Thermal Management
PRELIMINARY
CASE 3 Combined direct convection to the air and conduction to the PC board. A combination of cooling techniques that utilize the power planes and dissipation to the air will also reduce the total thermal impedance. This is the most effective cooling method.To estimate the total effect of the combination, treat each cooling branch as one leg of a parallel resistor network.
The high efficiency of the VTM results in low power dissipation minimizing temperature rise, even at full output current. The heat generated within the internal semiconductor junctions is coupled through very low thermal resistances, RJC and RJB (see Figure 25), to the PC board allowing flexible thermal management. CASE 1 Convection via optional Pin Fins to air (Pin Fins available mounted to the V*I Chip or as a separate item.) In an environment with forced convection over the surface of a PCB with 0.4" of headroom, a VTM with Pin Fins offers a simple thermal management option. The total Junction to Ambient thermal resistance of a surface mounted V048L015T80 is 5 C/W in 300 LFM airflow, (see Figure 26). At full rated current (80A) the VTM dissipates approximately 11 W. Power dissipation curves in Figure 6 show typical dissipation at different output currents.
Figure 25--Thermal resistance CASE 2 Conduction to the PC board The low thermal resistance, Junction to BGA, allows the use of the PC board as a means of removing heat from the VTM. Convection from the PC board to ambient, or conduction to a cold plate, enable flexible thermal management options. In this case, the VTM can be used without the Pin Fin option, allowing a system designer to take full advantage of the VTM's low profile. With a VTM mounted on a 2.0 in area of a multi-layer PC board with appropriate power planes resulting in 8 oz of effective copper weight, the Junction-to-ambient thermal resistance, RJA, is 6.5 C/W in 300 LFM of air. With a maximum junction temperature of 125C and 11 W of dissipation at full current of 80 A, the resulting temperature rise of 72C allows the VTM to operate at full rated current up to a 53C ambient temperature. See thermal resistance table on page 1 for additional details on this thermal management option. Adding low-profile heat sinks to the PC board can lower the thermal resistance of the PC board surrounding the VTM. This option is useful in environments that cannot accommodate the height of the Pin Fin option. Additional cooling may be added by coupling a cold plate to the PC board with low thermal resistance stand offs.
2
VTM with optional 0.25'' Pin Fins
10 9 8 7
Tja
6 5 4 3 0
100
200
300
400
500
600
Airflow (LFM)
Figure 26--Junction-to-ambient thermal resistance of VTM with 0.25" Pin Fins. (Pin Fins are available as an option for the V*I Chip package.)
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V*I Chip Voltage Transformation Module Rev. 1.6 Page 12 of 20
Application Note (continued)
V*I Chip VTM LEVEL 1 DC BEHAVIORAL MODEL for 48V to 1.5V, 80A
IOUT ROUT
1.2 m
1
+
/32 * Iout
+
V*I
1
VIN
IQ
52 mA
+ -
K
+ -
/32 * Vin
VOUT
-
-
(c)
Figure 27--This model characterizes the DC operation of the V*I Chip VTM, including the converter transfer function and its losses. The model enables estimates or simulations of output voltage as a function of input voltage and output load, as well as total converter power dissipation or heat generation.
V*I Chip VTM LEVEL 2 TRANSIENT BEHAVIORAL MODEL for 48V to 1.5V, 80A
0.4 nH
LIN = 20 nH
IOUT
ROUT
1.2 m
LOUT = 1.6 nH RCOUT
70 300 F
+
4.0 m
+
RCIN
1 F
1
/32 * Iout
V*I
0.9 m
1
CIN VIN
IQ
52 mA
+ -
K
+ -
/32 * Vin
COUT
VOUT
-
-
(c)
Figure 28--This model characterizes the AC operation of the V*I Chip VTM including response to output load or input voltage transients or steady state modulations. The model enables estimates or simulations of input and output voltages under transient conditions, including response to a stepped load with or without external filtering elements.
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V*I Chip Voltage Transformation Module Rev. 1.6 Page 13 of 20
Application Note (continued)
Using the VTM with a controlled DC source
PRELIMINARY
The VTM may be applied to provide a low output voltage at high current from a controlled 48V source. The overall efficiency of a power system based on Factorized Power Architecture, using VTMs, exceeds the efficiency of power systems based on Distributed Power Architecture, using DC-DC converters, or the Intermediate Bus Architecture, using non-isolated POL converters. The fast VTM transient response eliminates the need for large amounts of capacitance at the point of load (POL). Energy storage capacitors may be added at the input of the VTM, where they are more effective. Capacitors used at the VTM input get 2 reflected at the output multiplied by (1/K) . For example, a 1 F capacitor placed at the input of a VTM with a K=1/32 has the effective energy storage of 1,000 F at its output. Since the VTM has a 1 MHz bandwidth, only high frequency decoupling with ceramic capacitors is necessary at the POL, even with fast switching, dynamic loads. The following describes typical applications for a VTM powered from a 48 V source, such as DC-DC converters or PRMs.
The VTM has a very low output resistance, ROUT. This will cause the output voltage to change slightly with load current unless ROUT is compensated by a control loop.Without compensation, the output voltage of the VTM can be expressed as follows: VOUT = K * Vf - ROUT * ILOAD where Vf is the factorized bus input voltage to the VTM. For the V048K015T80, this equation becomes: VOUT = 1/32 * Vf - 0.0013 * ILOAD The voltage of the source may be set to a value that produces the desired VTM output voltage at the nominal load current: Vf = (VOUT + ROUT * INOM)/K ; = 32 * (VOUT + 0.0013 * INOM) The voltage of the source may be set by using trim up (Ru) or trim down (Rd) resistors or it may be actively controlled by a suitable voltage applied at a source voltage control node (SC).
Open Loop Application In an open loop implementation, the VTM is connected at the output of a DC-DC converter or controlled voltage source (Fig. 29). The no load output of the VTM is the voltage of the source multiplied by the K factor of the VTM. The K factor of the V048K015T80 is 1/32; hence, at 48 Vdc from the source, the VTM's output is 1/32 * 48V = 1.5 Vdc. The output of the VTM can be set over the range of 1.0 to 1.8 Vdc, at no load, and 0.9 to 1.7 V, at full load, by controlling the Vf of the source from 32 V to 57.6 V.
+Out +S DC-DC Converter SC or Voltage Source -S -Out Ru
+IN +OUT VTM K=1/32 - OUT -IN
V=K*Vf - ROUT * ILOAD
Vf
LOAD
Rd
Figure 29--Open loop operation with DC-DC converter or other controlled voltage source.
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V*I Chip Voltage Transformation Module Rev. 1.6 Page 14 of 20
Application Note (continued)
Closed Loop Application
PRELIMINARY
To compensate for the effect of the VTM's output resistance on the load voltage as a function of load current, a feedback loop can be implemented as shown in Fig.30. VTMs can also be used in a Factorized Power Architecture system with VID control of the output voltage as a faster, more efficient alternative to multiphase VRMs as shown in Fig.31. Off-line DC-DC converters, telecom input DC-DC converters and switching regulators may be adapted, through a suitable interface, to provide the PRM function.
High efficiency, high density PRMs in V*I Chip packages are in development. Please consult with Vicor application engineering for specific application information. Email:apps@vicr.com; phone: 1-800-927-9474
FPA Application Example
Unregulated Input Bus
PRM
Factorized Bus
Vf
VTM
Vf * K
Load
Figure 30--Basic Factorized Power Architecture with Pre-Regulation Module (PRM) and VTM
FPA Application Example
DC Distribution Bus
PRM
Vf = 32-58 Vdc
VTM 32:1
1.0-1.8 Vdc
P
VID Control
POL IC
Analog Control
Figure 31--PRM and VTM, Closed loop with VID Controller
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V*I Chip Voltage Transformation Module Rev. 1.6 Page 15 of 20
Application Note (continued)
V*I Chip Handling and Solderability
PRELIMINARY
The product should remain in its package in a dry environment until ready for use. The following table shows the soldering requirements for both the BGA in-board surface mount package and the J-lead on-board surface mount package.
The reflow process should use industry standard Surface Mount Technology (SMT) conditions. The exact conditions will depend upon the solder paste manufacturer's recommendations. Under no circumstance should the case temperature exceed 208C. Refer to Fig.32 for a suggested thermal profile.
Solder Paste Stencil Thickness Stencil Aperture Placement Acceleration Rate
BGA Package 63/37 "No Clean"* 4-6 mil 20 mil; 1:1 ratio Within 50% of pad center <500 in/sec2
J-Lead Package 63/37 "No Clean" 4-6 mil 0.8-0.9:1 ratio 5 mil <500 in/sec2
*Halide free water washable 63/37 Flux paste can be used for the BGA version package only. Please consult our Application Engineers for further information.
Figure 32--Thermal profile diagram
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V*I Chip Voltage Transformation Module Rev. 1.6 Page 16 of 20
Application Note (continued)
Input Impedance Recommendations
PRELIMINARY
Input Fuse Recommendations V*I Chips are not internally fused in order to provide flexibility in power system configuration. However, input line fusing of V*I Chips must always be incorporated within the power system. A fast acting fuse, such as NANO2 FUSE 451 Series 7 A 125 V, is required to meet safety agency Conditions of Acceptability. The input line fuse should be placed in series with the +IN port.
To take full advantage of the VTM's capabilities, the impedance of the source (input source plus the PC board impedance) must be low over a range from DC to 5 MHz. The input of the VTM should be locally bypassed with a 8 F low Q aluminum electrolytic capacitor. Additional input capacitance may be added to improve transient performance or compensate for high source impedance. The VTM has extremely wide bandwidth so the source response to transients is usually the limiting factor in overall output response of the VTM. Anomalies in the response of the source will appear at the output of the VTM, multiplied by its K factor of 1/32. The DC resistance of the source should be kept as low as possible to minimize voltage deviations on the input to the VTM. If the VTM is going to be operating close to the high or low limit of its input range, make sure input voltage deviations will not trigger the under or over voltage shutdown.
Warranty Vicor products are guaranteed for two years from date of shipment against defects in material or workmanship when in normal use and service. This warranty does not extend to products subjected to misuse, accident, or improper application or maintenance. Vicor shall not be liable for collateral or consequential damage. This warranty is extended to the original purchaser only. EXCEPT FOR THE FOREGOING EXPRESS WARRANTY, VICOR MAKES NO WARRANTY, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Vicor will repair or replace defective products in accordance with its own best judgement. For service under this warranty, the buyer must contact Vicor to obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be returned to the buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was defective within the terms of this warranty. Information published by Vicor has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. Vicor reserves the right to make changes to any products without further notice to improve reliability, function, or design. Vicor does not assume any liability arising out of the application or use of any product or circuit; neither does it convey any license under its patent rights nor the rights of others. Vicor general policy does not recommend the use of its components in life support applications wherein a failure or malfunction may directly threaten life or injury. Per Vicor Terms and Conditions of Sale, the user of Vicor components in life support applications assumes all risks of such use and indemnifies Vicor against all damages.
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V*I Chip Voltage Transformation Module Rev. 1.6 Page 17 of 20
NOTES
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V*I Chip Voltage Transformation Module Rev. 1.6 Page 18 of 20
NOTES
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V*I Chip Voltage Transformation Module Rev. 1.6 Page 19 of 20
Vicor's comprehensive line of power solutions includes high density AC-DC and DC-DC modules and accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom power systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor components are not designed to be used in applications, such as life support systems, wherein a failure or malfunction could result in injury or death. All sales are subject to Vicor's Terms and Conditions of Sale, which are available upon request.
Specifications are subject to change without notice. Intellectual Property Notice
Vicor and its subsidiaries own Intellectual Property (issued U.S. and Foreign Patents and pending patent applications) relating to the product described in this data sheet including; * The electrical and thermal utility of the V*I Chip package * The design of the V*I Chip package * The Power Conversion Topology utilized in the V*I Chip package * The Control Architecture utilized in the V*I Chip package * The Factorized Power Architecture. Purchase of this product conveys a license to use it. However, no responsibility is assumed by Vicor for any infringement of patents or other rights of third parties which may result from its use. Except for its use, no license is granted by implication or otherwise under any patent or patent rights of Vicor or any of its subsidiaries. Anybody wishing to use Vicor proprietary technologies must first obtain a license. Potential users without a license are encouraged to first contact Vicor's Intellectual Property Department.
Vicor Corporation 25 Frontage Road Andover, MA, USA 01810 Tel: 800-735-6200 Fax: 978-475-6715 Email Vicor Express: vicorexp@vicr.com Technical Support: apps@vicr.com
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V*I Chip Voltage Transformation Module Rev. 1.6 P/N 26800 11/03/10M Page 20 of 20

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